Computer processor design is an extremely complex and lengthy process. The design process includes a range of tasks from high level tasks such as specifying the architecture down to low level tasks such as determining the physical placement of transistors on a silicon substrate. Each stage of the design process also involves extensive testing and verification of the design through that stage. One typical stage of processor design is to program the desired architecture for the processor using a register transfer language (RTL). The desired architecture is represented by an RTL specification that describes the behavior of the processor in terms of step-wise register contents. This simulates what the processor does without describing the physical circuit details. Thus, the architecture can be verified at a high level, independent of implementation details such as circuit design and transistor layout. The RTL specification also facilitates later hardware design of the processor.
However, manually verifying the RTL specification of the processor architecture would be prohibitively complex during the design of a modern microprocessor. Multiple test cases are typically generated to test the design. Each test case contains input instructions and may also contain the desired results or outputs. Rather than running test cases through a simulation of the RTL specification and manually verifying the results, the test cases may be executed both on a simulation of the RTL specification (often compiled to increase speed), and on a “golden simulator”, with the results compared. The golden simulator is simply another simulation of the processor architecture which has a higher likelihood of accurately implementing the desired architecture than the RTL specification. The golden simulator may be implemented in any desired manner, such as a custom program written using a high-level programming language. The golden simulator is often a higher-level implementation of the processor architecture than the RTL specification, although the golden simulator typically does go into enough detail to match the major structures in the RTL specification. For example, if the RTL specification describes a translation lookaside buffer (TLB), the golden simulator should also implement a TLB to enable full testing and comparison of the RTL specification.
Test cases may thus be executed both on the RTL specification and the golden simulator, with the results compared. Any difference in the results indicates an error in the RTL simulation, the golden simulator, or both, although in theory the golden simulator is more likely to be error-free than the RTL simulation.
Custom tools such as the golden simulator are complex and expensive and may be reused for entire families of product lines all based on the same architecture. However, if the processor design is changed, it can be expensive to adapt or rewrite the tools. For example, if an updated processor design communicates through a new type of output interface, the golden simulator may be rendered useless, even if the underlying architecture matches that in the golden simulator. If the output of the RTL specification is in the new output format, the golden simulator is either modified to also produce the new output format or is replaced.